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INIC-1510 initio corporation 1 INIC-1510 usb to pata bridge specification version 1.0 march 30, 2006 initio corporation
INIC-1510 initio corporation 2 change history: 3/30/06 - release
INIC-1510 initio corporation 3 table of contents 1. introduction ............................................................................................................................... .... 4 1.1 feature summary ???????????????????????????....4 1.2 firmware/software support ????????????????????????.4 1.3 devices support ????????????????????????????...4 2. usb to ata block diagram ......................................................................................................... 5 3. pin signal description: (64-pin package) ...................................................................................... 6 3.1 usb interface ?????????????????????????????..6 3.2 serial flash interface ??????????????????????????6 3.3 ata interface (driving current 4ma-10 ma controlled by register a8[1:0]) ????..6 3.4 system interface ????????????????????????????.7 3.5 gpio interface ?????????????????????????????7 3.6 power regulator pins ??????????????????????????.7 3.7 power/gnd ??????????????????????????????7 3.8 64-pin diagram ?????????????????????????..???..8 4. firmware program/download procedure ????????????????????.. ?????... 9 5. register address mapping ???????????????????????.. ????????... 10 5.1 usb block ??????????????????????????????10 5.2 ata block ??????????????????????????????11 5.3 cmd/data block ?????.......................................................................................12 5.4 dma block ?????????????????????????????...12 5.5 data space mapping ?????????????????????????????........... 12 6. register descriptions ?????????????????????.. ?????????????. 12 7. electrical information ??????????????????????????????????... 25 7.1 absolute maximum ratings ???????????????????????25 7.2 recommended operating conditions ???????????????????..25 7.3 general dc characteristics ?????..........................................................................25 7.4 dc electrical characteristics for 3.3v operation ???????????????.25 8. packaging specification ............................................................................................................... 26
INIC-1510 initio corporation 4 1. introduction: the INIC-1510 provides an advanced solution to c onnect atapi or eide devices to usb interface with integrated cpu and embedded sram. to provide high performance and cost effective solution, the INIC-1510 integrates usb-phy, ma ss storage class bulk-o nly usb function, ata control block and microprocessor in to a single asic. the INIC-1510 pr ovides the data transfer rate of up to 60 mb/sec; its ata interface suppor ts ultra dma modes up to 100 mb/sec. 1.1 feature summary ? usb mass storage class bulk-only specification-compliant (version 1.0) ? two bulk endpoints(in and out) and one interrupt endpoint(in) ? t13 1410d ata/atapi-6 compliant (3.3 v with 5v tolerance) ? support dma mode 0-2, and udma mode 2, 3, 4 and 5 (up to 100mb/s) ? integrated internal cpu with embedded sram ? implement the firmware download mechanism ? low power cmos with 3.3volts ? 64-pin lqfp package 1.2 firmware/software support ? usb mass storage class bulk-only transport support ? provide software utilities for downl oading the upgraded firmware code 1.3 devices support ? hard disk drives ? cd-rw devices ? dvds ? removable media devices.
INIC-1510 initio corporation 5 2. usb to ata block diagram: figure 1: INIC-1510 block diagram data fifo disk data flow control command/status block scratch sram ata dma/ udma control block control registers block u p 8032 sflash interface serial flash 64 kbytes usb phy usb core usb port
INIC-1510 initio corporation 6 3. pin signal descript ion: (64-pin package) 3.1 usb interface signal name pin number i/o driver type description dp 21 i/o usb high /full speed buffer (d+) high/full speed d+ signal dm 20 i/o usb high/full speed buffer (d-) high/full speed d- signal rref 19 a power pll voltage reference. current source for 330r(1%) resistor connected to avss vbus 10 i piw active high. indicates that vbus is present. xin 15 i a crystal oscillator input (12mhz) xout 16 o a crystal oscillator output (12mhz) 3.2 serial flash interface signal name pin number i/o driver type description scen /gpiof7 9 i/o pbu16w serial flash chip enable sd /gpiof6 8 i/o pbu16w serial flash data input/output sck /gpiof5 7 i/o pbu16w serial flash clock 3.3 ata interface (driving current 4ma-10 ma controlled by register a8[1:0]) signal name pin number i/o driver type description dd[15:0]/ gpiod[7:0], gpioc[7:0] 37, 40, 42, 44, 46, 48, 52, 54, 53, 51, 47, 45, 43, 41, 38, 36 i/o pbscudsl ata data bus da[2:0] /gpioe[2:0] 29, 28, 27 i/o pbscudsl device address reset0# /gpiob6 60 i/o pbscudsl reset 0(out) dcs0[1:0]# /gpioe[4:3] 58, 55 i/o pbscudsl ata device chip select 0(out) dmarq0 34 i/o pbscudsl dma request 0(in) dmack0# /gpiob1 30 i/o pbscudsl dma acknowledge 0(out)
INIC-1510 initio corporation 7 diow0# /gpiob3 33 i/o pbscudsl i/o write 0(out) dior0# /gpiob2 32 i/o pbscudsl i/o read 0(out) iordy0 /gpioe5 31 i/o pbscudsl i/o ready 0(in) ataintr0 59 i/o pbscudsl ata interrupt 3.4 system interface signal name pin number i/o driver type description porst# 2 i pisw power on reset. when this signal is active, all of pins on ata interface should be tri-stated. testmode[1:0 ] 26, 25 i pid test mode select 00-> normal operation mode 01-> usb-bist 10-> mbist 11-> scan 3.5 gpio interface signal name pin number i/o driver type description p1.[2:0] p1.4 61, 62, 1, 3 i/o pb16w up8032 i/o port 1, can be used as extra gpios p3.[1:0] p3.3 4, 5, 6 i/o pb16w up8032 i/o port 3. can be used as extra gpios 3.6 power regulator pins signal name pin number i/o driver type description reg_vcc33 12 i total 1 pin reg_gnd 11 i total 1 pin reg_v18out 13 o total 1 pin 3.7 power/gnd signal name pin number i/o driver type description vcc3 35, 50, 57 io 3.3v vss3 39, 49, 56 io gnd vdd1p8 23, 64 core 1.8v vss1p8 24, 63 core gnd vd33 17 3.3v, for vdd33p and vd33 vs33p 18 usb io cell gnd vdda 14 1.8v for pll vssa 22 vssa for pll
INIC-1510 initio corporation 8 3.8 64-pin diagram | | | | | | | | | | | | | | | | v v r d d v v v t t d d d d i d d s r m p s d s e e a a a m o i 3 3 e s d s s s 0 1 2 a r o 3 3 f a 1 1 t t c d r p p p m m k y 0 8 8 o o 0 0 # d d # e e 0 1 p1.1 --- 1 porst# --- 2 p1.0 --- 3 p3.3 --- 4 p3.1 --- 5 p3.0 --- 6 sck --- 7 sd --- 8 scen --- 9 vbus --- 10 reg_gnd --- 11 reg_vcc33 -- 12 reg_v18out -- 13 vdda --- 14 xin --- 15 xout --- 16 48 --- dd10 _ _ 47 --- dd5 46 --- dd11 45 --- dd4 44 --- dd12 43 --- dd3 42 --- dd13 41 --- dd2 40 --- dd14 39 --- vss3 38 --- dd1 37 --- dd15 36 --- dd0 35 --- vcc3 34 --- dmarq0 33 --- diow0# v v p p r a d v v d d d d d v v d s 1 1 e t c c s c d d d d c s d s . . s a s c s s 8 7 9 6 c s 1 1 2 4 e i 0 3 3 0 3 3 p p t n 1 0 8 8 0 t # r 0 | | | | | | | | | | | | | | | | 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9
INIC-1510 initio corporation 9 4. firmware program/download procedure 1. host send read_chip_id packet through control channel to read chip-id, which is 0x29c5_1510 here. 2. host send hold_cpu packet through control channel to set hold_cpu bit. 3. host may send flash_write/flash_read/data_write/data_read packet through control channel to write/read flash or data space. host may program and read serial flash memory through de fault endpoint. flash writ e setup packet format is: offset field size value description 0 bmreqtype 1 0x40 vendor write 1 breq 1 flash write [7]: 0?flash memory [6]: 1?addr valid [5]: 1?data valid [4:0]: 5?h01?flash write 2 addr[7:0] 3 wvalue 2 addr[15:0] address to be written 4 opcode 5 windex 2 data[7:0] flash data 6 0x00 7 wlength 2 0x00 flash read setup packet format is: offset field size value data description 0 bmreqtype 1 0xc0 vendor read 1 breq 1 flash read [7]: 0?flash memory [6]: 1?addr valid [5]: 1?data valid [4:0]: 5?h02?flash read 2 addr[7:0] 3 wvalue 2 addr[15:0] address to be written 4 opcode 5 windex 2 0x00 don?t care 6 0x01 7 wlength 2 0x00 data from flash read_chip_id setup packet format is: offset field size value data description 0 bmreqtype 1 0xc0 chip-id vendor read
INIC-1510 initio corporation 10 1 breq 1 0x03 2 0x00 3 wvalue 2 0x00 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x04 7 wlength 2 0x00 0x10, 0x15, 0xc9, 0x25 hold_cpu setup packet format is: offset field size value description 0 bmreqtype 1 0x40 vendor write 1 breq 1 0x04 hold_cpu 2 0x00 3 wvalue 2 0x00 don?t care 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x00 don?t care 7 wlength 2 0x00 don?t care 5. register address mapping: 5.1 usb block (address area: 60xx) address read value write value 20h dev_status dev_status 21h funct_adr funct_adr 22h test_mode test_mode 25h eptxlength[7:0] eptxlength[7:0] 26h eptxlength[15:8] eptxlength[15:8] 30h ep0_status ep0_ control (set) 31h ep0_status ep0_ control (clear) 32h ep0_status2 ep0_ control 2(set) 33h ep0_status2 ep0_ control 2(clear) 34h ep0txlength ep0txlength 38-3f hdr0-7 - 40h ep1_status ep1_ control (set) 41h ep1_status ep1_ control (clear) 50h ep2_status ep2_ control (set) 51h ep2_status ep2_ control (clear) 52h usb_rxlength[7:0] - 53h usb_rxlength[15:8] - 60h ep3_status ep3_ control (set) 61h ep3_status ep3_ control (clear) 70h totalcnt0 totalcnt0 71h totalcnt1 totalcnt1 72h totalcnt2 totalcnt2 73h totalcnt3 totalcnt3 74h - loadtotalcnt 80h gtotalcnt0 gtotalcnt0
INIC-1510 initio corporation 11 81h gtotalcnt1 gtotalcnt1 82h gtotalcnt2 gtotalcnt2 83h gtotalcnt3 gtotalcnt3 5.2 ata block: (address area: 40xx) address read value write value 90h data[7:0] data[7:0] 91h error features 92h sectorcount sectorcount 93h sectornumber sectornumber 94h cyclinderlow cylinderlow 95h cylinderhigh cylinderhigh 96h device/head device/head 97h status command 98h reserved reserved 99h reserved reserved 9ah reserved reserved 9bh reserved reserved 9ch reserved reserved 9dh reserved reserved 9eh alternatestatus devicecontrol 9fh reserved reserved a0h fifo0d[7:0] fifo0d[7:0] a2h sgpctl sgpctl a3h fifost fifost a4h gpiodata gpiodata a5h gpioctl gpioctl a6h testctl0 testctl0 a8h drvctl drvctl ach upctl upctl afh miscctl miscctl (internal testing) b0h linkctl linkctl b1h dmactl dmactl b4h sgdctl sgdctl_set b5h sgdctl sgdctl_clr b6h atactl atactl b7h atastatus atastatus bdh spi_status spi-ctrl beh spi_rddata spi-wrdata bfh spi_command spi-command c0h,c2h-ceh rdata[7:0] wdata[7:0] c1h,c3h-cfh rdata[ 15:8] wdata[15:8] d6h ata_status_hi ata_status_hi d7h ata_status_lo ata_status_lo d8h usbint_en usbint_en d9h usbint_status usbint_clr dch gpioa_int_en gpioa_int_en ddh spi_adr[7:0 ] spi_adr[7:0] deh spi_adr[15:8] spi_adr[15:8] dfh spi_adr[31:16] spi_adr[31:16]
INIC-1510 initio corporation 12 f2h gpiob_din[7:0] gpiob_dout[7:0] f3h gpiob_ctrl[7:0] gpiob_ctrl[7:0] f4h gpioc_din[7:0] gpioc_dout[7:0] f5h gpioc_ctrl[7:0] gpioc_ctrl[7:0] f6h gpiod_din[7:0] gpiod_dout[7:0] f7h gpiod_ctrl[7:0] gpiod_ctrl[7:0] f8h gpioe_din[7:0] gpioe_dout[7:0] f9h gpioe_ctrl[7:0] gpioe_ctrl[7:0] fah gpiof_din[7:0] gpiof_dout[7:0] fbh gpiof_ctrl[7:0] gpiof_ctrl[7:0] note : 1. every read operation from any of 9xh registers needs to be followed by another read operation on c0h. 2. register c1h is used for accessing the high byte of 16-bit pio data. 5.3 cmd/data block: (address area: 40xx) address read value write value 100h-13fh (64 bytes) cmdrx0buffer can not be written by cpu 140h-17fh (64 bytes) cmdrx1buffer can not be written by cpu 1c0h-1efh (64 bytes) cmdtx1buffer cmdtx1buffer 240h-26fh (64 bytes) cmdtx3buffer cmdtx3buffer 280h-2afh (64 bytes) cmdtx4buffer cmdtx4buffer 5.4 dma block: (address area: 40xx) address read value write value 500h-53fh sglist[3:0] sglist[3:0] 5.5 data space mapping mapping address type access type mapping block 0000h-3fffh data read/write internal sram (16kb) 4000h-47ffh data read/write internal register/buffers 5000h-5fffh data read/write sgbuffer (4kb) 6000h-60ffh data read/write usb registers 8000h-ffffh data read/write external sram (32kb) 6. register descriptions: the following are usb registers, based on 0x6000 6.1.1 device status (dev_status[7:0], 0x20)
INIC-1510 initio corporation 13 field name rscu bit # reset description rsvd r 7 1?b0 reserved test_mode rsu 6 1?b0 set when set_feature (test_mode). exit by cycle vbus. attach ru 5 1?b1 hardware reset default state. clear if detect vbus valid. then set power bit powered ru 4 1?b0 set if vbus=1 & previous state is attach. or , power interruption. suspend ru 3 1?b0 after bus idle for sometime, hardware set this bit. when resume detected, hardware reset this bit and return to previous state default ru 2 1?b0 after bus rese t, hardware set this bit. addressed rscu 1 1?b0 set_addr ess or set_configuration(0) configured rscu 0 1?b0 set_configuration 6.1.2 function address (funct_adr[7:0], 0x21) field name rscu bit # reset description rsvd ru 7 1?b0 reserved adr ru 6:0 7?b0 set_address 6.1.3 test mode (test_mode[7:0], 0x22) field name rscu bit # reset description rsvd ru 7:4 4?b0 reserved test_mode rwu 3:0 4?b0 test mode se lectors(table 9-7, usb2.0 spec) 4?h1: test_j 4?h2: test_k 4?h4: test_se0_nak 4?h8: test_packet others: rsvd 6.1.4 end point tx data length low bytes (ep_txlength[7:0], 0x25) field name rscu bit # reset description ep_txlength rwu 7:0 8?b0 for ep1 (bulk_in): for ata-command-no-dma-involved, this field indicates how many bytes sent back to host. maximum 512-bytes 6.1.5 end point tx data length high bytes (ep_txlength[15:8], 0x26) field name rscu bit # reset description rsvd r 7:2 6?b0 reserved ep_txlength rwu 1:0 2?b0 high bytes
INIC-1510 initio corporation 14 6.1.6 end point 0 status/control (ep0_sta tus[7:0], 0x30: set, 0x31: clear) field name rscu bit # reset description suspend_gnt rsc 7 1?b0 suspend-request granted usb_busrst rcu 6 1?b0 set by hardware after an usb bus reset detected . clear by firmware. bulk_only_rst rcu 5 1?b0 set by hardware, read an d cleared by firmware after firmware responds bulk-only-reset command done. rsvd ru 4:3 2?b0 reserved ep0_speed ru 2 1?b0 1?hs, 0--fs remote_wakeup rscu 1 1?b0 set/clr by firmware. remote wakeup request. halt rscu 0 1?b0 1-ep0 halt. function stall. device reset is require to clear this bit 6.1.7 end point 0 status/control2 (ep1_status2 [7:0], 0x32: set, 0x33: clear, bulk-in) field name rscu bit # reset description fw_rdy rsc 7 1?b0 0: default valu e as no firmware installed. hard ware response all control packet for firmware download in most case. 1: firmware controls some setup packet response. rsvd r 6:4 3?b0 reserved ep0_statrun rsu 3 1?b0 set by firmware if devi ce ready to go to control status stage. ep0_out rcu 2 1?b0 set by hardware if a control co mmand-data is received. clear by firmware after processing. ep0_run rsu 1 1?b0 set by firmware. when firmware se t this bit, the data will be transferred from data buffer to usb. how many bytes transferred is based on the data transfer length in the ep_txlength( 0x25, 0x26) ep0_setup rcu 0 1?b0 set by hardware if a contro l command is received. clear by firmware after processing. 6.1.8 end point tx data length low bytes (ep0txlength[7:0], 0x34) field name rscu bit # reset description rsvd r 7 1?b0 reserved ep0txlength rwu 6:0 7?b0 for ep0 (control): this fi eld is filled by firmware . when firmware taking control setup packet response, firmware write this fiel d to inform hardware the data length to be send back to host. maximum 64-bytes. 6.1.9 setup packet (hdr0?hdr7[7:0], 0x38?0x3f) field name rscu bit # reset description hdr ru 7:0 8?bx 8 bytes setup packet. 6.1.10 end point 1 status/control (ep1_status[7: 0], 0x40: set, 0x41: clear, bulk-in)
INIC-1510 initio corporation 15 field name rscu bit # reset description gtotalcnteq 0 r 7 0 1-> ata global totalcnt equ 0 0-> else totalcnteq0 r 7 0 1-> ata totalcnt equ 0 0-> else rsvd r 5:4 4?b0 reserved csw_run rscu 3 1?b0 set by firmware when firmware ready to send csw. clear by hardware after csw is sent successfully. rsvd r 2 1?b0 reserved ep1_run rscu 1 1?b0 set by firmware. when firmware set this bit, the data will be transferred from data buffer to usb. how many bytes transferred is based on the data transfer length in the ep_txlength( 0x25, 0x26) halt rscu 0 1?b0 1-ep1 halt. 6.1.11 end point 2 status/control (ep2_status[ 7:0], 0x50: set, 0x51 clear, bulk-out) field name rscu bit # reset description fs_en rw 7 1?b0 1-> force devi ce to full speed mode only rsvd r 6:3 5?b0 reserved ep2_rx rcu 2 1?b0 set by hardware after the bulk out packet received. th e number of total data length received will be shown in usb_rxl ength register. this bit is used by firmware to monitor the data transfer between usb and internal data buffer. this bit is cleared by firmware or automatically cleared by hardware after the next cbw received or sg0r un bit set by firmware. ep2_cbw rcu 1 1?b0 set by hardware if a valid cbw received. clear after processing by firmware. halt rscu 0 1?b0 1-ep2 halt. 6.1.12 usb_rxlength(usb_rxlength[7:0], 0x52, bulk-out) field name rscu bit # reset description rxlength rwu 7:0 8?b0 the low byte of data length re ceived. this register is used to show how many date received from usb to in ternal data buffer. 6.1.13 usb_rxlength(usb_rxlength[11:8], 0x53, bulk-out) field name rscu bit # reset description rxlength rwu 7:0 8?b0 the high byte of data length re ceived. this register is used by firmware to show how many data received from us b to internal data buffer. 6.1.14 end point 3 status/control (ep3_status[7: 0], 0x60: set, 0x61: clear, intr-in) field name rscu bit # reset description
INIC-1510 initio corporation 16 rsvd r 7:3 5?b0 reserved ep3_run rsu 2 1?b0 1?packet ready. cleared by hardware after tx completed rsvd r 1 1?b0 reserved halt rscu 0 1?b0 1-ep3 halt. 6.1.15 end point tx data length low bytes (ep3txlength[7:0], 0x62) field name rscu bit # reset description rsvd r 7 1?b0 reserved ep3txlength rwu 7:0 7?b0 for ep3 (int_in): this field is filled by firmware. firmware writes this field to inform hardware the data length to be sent back to host. maximum 64- bytes. 6.1.16 total count0 (totalcnt[7:0], 0x70 totalcnt0) field name rscu bit # reset description totalcnt0 rwu 7-0 8?b0 totalcnt[7:0] 6.1.17 total count1 (totalcnt[15:8], 0x71 totalcnt1) field name rscu bit # reset description totalcnt1 rwu 7-0 8?b0 totalcnt[15:8] 6.1.18 total count2 (totalcnt[23:16], 0x72 totalcnt2) field name rscu bit # reset description totalcnt2 rwu 7-0 8?b0 totalcnt[23:16] 6.1.19 total count3 (totalcnt[31:24], 0x73 totalcnt3 ) field name rscu bit # reset description totalcnt3 rwu 7-0 8?b0 totalcnt[31:24] 6.1.20 load total count (load totalcnt, 0x74 ) field name rscu bit # reset description reserved r 7-1 7?b0 reserved loadtotalcnt w 0 1?b0 write an 1 to this bit will re-load the value from register 0x73-0x70?s totalcnt[31:0] to internal counter.
INIC-1510 initio corporation 17 6.1.21 global total count0 (gtotalcnt[7:0], 0x80 gtotalcnt0) field name rscu bit # reset description gtotalcnt0 rwu 7-0 8?b0 gtotalcnt[7:0] 6.1.22 global total count1 (gtotalcnt[15:8], 0x81 gtotalcnt1) field name rscu bit # reset description gtotalcnt1 rwu 7-0 8?b0 gtotalcnt[15:8] 6.1.23 global total count2 (gtotalcnt[23:16], 0x82 gtotalcnt2) field name rscu bit # reset description gtotalcnt2 rwu 7-0 8?b0 gtotalcnt[23:16] 6.1.24 global total count3 (gtotalcnt[31:24], 0x83 gtotalcnt3 ) field name rscu bit # reset description gtotalcnt3 rwu 7-0 8?b0 gtotalcnt[31:24] the following are general registers, and are in address area: 40xx 6.2.1 fifo 0 data register (fifo0d[7:0], 0x0a0) field name rscu bit # reset description fifo0data rw 7:0 8?h0 dma fifo 0 data register . software can access dma fifo 0 through this register. 6.2.2 sgpiocmd control register (sgpctl, 0x0a2) field name rscu bit # reset description reserved r 7-1 6?b0 reserved. pio0run rw 0 1?b0 after set. before set this bit, the firmware needs to di sable atadmaen bit on dma control register, write the package header into the segment of sgcmd buffer, set run bit on sgcmd control regi ster, and fill data into fifo data register. 6.2.3 fifo status register (fifost, 0x0a3) field name rscu bit # reset description reserved r 7-1 6?b0 reserved. fifo0rst rw 0 1?b0 dma fifo 0 reset. this bit is used to reset dma fifo 0. this bit is self- cleared by hardware after set.
INIC-1510 initio corporation 18 6.2.4 gpio data register (gpiodata, 0x0a4) field name rscu bit # reset description vbus r 7 1?b0 read: usb?s vbus status atarst0# w 6 1?b1 ata channel 0 reset signal. when clear, it will reset the ata device. gpiod[5:0] rw 5-0 6?h0 write: gpioout[5:0], read: gpioin[5:0] 6.2.5 gpio control register (gpioctl, 0x0a5) field name rscu bit # reset description gpioen rw 7 1?b0 gpio mode enable. reserved r 6 1?b0 reserved. gpioctl[5:0] rw 5-0 6?h0 general purpose i/o cont rol 5-0. when set, the gpio data is output. 6.2.6 test control 0 register (testctl0, 0x0a6) field name rscu bit # reset description rstatareq_ rw 7 1?b0 ata request reset. when set, it will reset the current ata request. reserved rw 6 1?b0 reserved. revid r 5-4 2?h0 revision id. these 2 bits are read only. reserved rw 6 1?b0 reserved. 6.2.7 ata i/o cell driving contro l register (drvctl, 0x0a8) field name rscu bit # reset description cfen rw 7 1?b0 compact flash mode enable. wh en set, the ata engine will run in pseudo dma mode enabling fast compact flash access. cfreq rw 6 1?b0 compact flash request. when set, it indicates to the ata engine that compact flash has requested data transfer. reserved r 5-3 4?h0 reserved. atatsen rw 2 1?b0 ata bus tristate enable. clear this bit to 0 will put the ini1430 ata bus in tristate mode. drvsel rw 1-0 2?h3 ata output driving: 00: 4 ma 01: 6 ma 10: 8 ma 11: 10 ma 6.2.8 up control register (upctl, 0x0ac) field name rscu bit # reset description reserved r 7-2 6?b0 reserved. usbwakeupen rw 1 1?b0 1-> enable external interrupt wake up host reserved r 0 1?b0 reserved. 6.2.9 miscctl register (0x0af) field name rscu bit # reset description reserved rw 7 1?b0 reserved. newmode rw 6 1?b0 0: inic1530 mode 1: enhance mode
INIC-1510 initio corporation 19 set_usbclken rw 5 1?b0 1: usb clock free run enum rw 4 1?b1 0: disconnect device from usb host hiden rw 3 1?b0 0: endp will be in(1)out(2)intr(3) 1: endp will be in(8)out(2)intr(1) reserved rw 2:0 3?b0 reserved. 6.2.10 sgcmd definition figure 2: sgcmd format field name width quadlet bit # description l. seg 1 1 21 if the command is the last one of s/g segments, this bit should be set by firmware. more 1 1 20 if the number of commands in sgcmd buffer is more than one, this bit should be set by firmware. dir 1 1 19 when 0, the dma data are transferred from p1394 bus to ata device. when 1, the dma data are tran sferred from ata device to p1394 bus. 6.2.11 link control register (linkctl, 0x0b0) field name rscu bit # reset description reserved r 7-1 6?b0 reserved. softreset rwu 0 1?b0 when set to 1, all host contro ller state is reset, all fifo?s are flushed, and host controller registers is reset. the read value of this bit is 1 while a soft reset or hard reset is in progress. the read value of this bit is 1 when ne ither soft reset nor hard reset is in progress. software can use the value of his bit to determine when a reset has completed and the host controller is safe to operate. 6.2.12 dma control register (dmactl, 0x0b1) field name rscu bit # reset description reserved r 7-4 1?h0 reserved. reserved reserved datalength sglist[ 3-0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved dir mo re l. seg
INIC-1510 initio corporation 20 diow# rw 3 1?b1 when dma fifo is underrun, this bit is used by firmware to toggle diow# signal. dior# rw 2 1?b1 when dma fifo is underrun, this bit is used by firmware to toggle dior# signal. dmack# rw 1 1?b1 when dma fifo is underrun, this bit is used by firmware to toggle dmack# signal. flush/abort rw 0 1?b0 when dma fifo is overrun, this bit is used by firmware to flush data out for outgoing data or abort the dma operation for incoming data. this bit is self-cleared by hardware. 6.2.13 channel clear register (cmdctl_clr, 0x0b3) field name rscu bit # reset description reserved r 7 7?b0 reserved cmdtx4run (for hid_out) rwu 6 1?b0 when the clear register is set by software, the corresponding channel is cleared. cmdtx3run (for csw_out) rwu 5 1?b0 when the clear register is set by software, the corresponding channel is cleared. reserved r 4 1?b0 reserved cmdtx1run (for control_out) rwu 3 1?b0 when the clear register is set by software, the corresponding channel is cleared. reserved r 2 1?b0 reserved cmdtx1run (for cbw) rwu 1 1?b0 when the clear register is set by software, the corresponding channel is cleared. cmdtx1run (for setup-packet) rwu 0 1?b0 when the clear register is set by software, the corresponding channel is cleared. 6.2.14 sgdma control register (sgctl_s et, 0x0b4) (sgctl_clr, 0x0b5) field name rscu bit # reset description reserved r 7:1 7?b0 reserved. sg0run rwu 0 1?b0 when set register is set by so ftware, the corresponding channel is ready to be transmitted. the hardware clears these bits when the transfer is completed. software can set bit[3:0] on clear regi ster to clear the corresponding bit. when clear register is written by software, the dma channels will be reset to idle. (usb bulk transfer will only use sg0run) 6.2.15 ata control register (atactl, 0x0b6) field name rscu bit # reset description atadmaen rw 7 1?b1 when 1, atadma is enabled. pioreq/piognt rw 6 1?b0 write 1 for pio request. pio grant status when read. dmamode rw 5 1?b0 0-2: dma mode 0 - 2 rw 4 1?b0 4-7: udma mode 2, 3, 4 and 5 (up to udma100) rw 3 1?b0 piomode rw 2 1?b0 0-4: pio mode 0-4 rw 1 1?b0 rwu 0 1?b0 6.2.16 ata control/status register (atastatus, 0x0b7) field name rscu bit # reset description reserved rw 7 1?b reserved
INIC-1510 initio corporation 21 0 atach01en rw 6 1?b 0 ata channel 0 &1 enable. when set, dma write to channel 0 & 1 will be executed simultaneously. pioxen rw 5 1?b0 pio transfer engine enable. when set, the pio engine will transfer data to/from the ata bus using pio transfer mechanism. reserved r 4 1?b0 reserved. reserved ru 3 1?b x reserved ataiordy0 ru 2 1?b x ata channel 0 iordy line. reserved ru 1 1?bx reserved ataintrq0 ru 0 1?bx ata channel 0 intrq line. 6.2.17 spi_ctrl/status register (0x0bd) (for spi-serial flash only) field name rscu bit # reset description startcmd w 7 1?b0 1: cpu write 1 to start the serial flash?s command phase reserved r 6-5 2?b0 startwrsr rw 4 1?b0 1: cpu write 1 to start the serial flash?s write_status_register action reserved r 3-2 2?b0 spi_wrdone r 1 1?b0 read only: cpu has send out the serial write command to serial flash. cpu may start sending out the read_status_command (rdsr) to serial flash to check the busy bit. when busy bit is 0, it means serial flash has finished the write operation. spi_rddatardy r 0 1?b0 read only: cpu has send out the serial read command to serial flash. 6.2.18 spi_data register (0x0be) (for spi-serial flash only) field name rscu bit # reset description spi_data rw 7-0 8?h0 this is the data port for cpu to access aerial flash a: to write to serial flash: cpu writes to this port: cpu writes a 8-bit data to serial flash. b: to read from serial flash: cpu reads this port: cpu does 1 st read: cpu activates the read action to fetch data from serial flash. cpu poll spi_rddatardy (register bd bit 0) until it is 1 cpu does 2nd read: to actually get the data. 6.2.19 spi_cmd register (0x0bf) (for spi-serial flash only) field name rscu bit # reset description spi_cmd rw 7-0 8?h0 cpu writes the to-be excuted spi_command code in this register. for example: spi_read has a command code: 03h
INIC-1510 initio corporation 22 6.2.20 ata_status_low register (0x0d6) field name rscu bit # reset description ata_status[7:0] rw 7-0 8?h0 cpu writes the ata status to this register 6.2.21 ata_status_high register (0x0d7) field name rscu bit # reset description ata_status[15:8] rw 7-0 8?h0 cpu writes the ata status to this register 6.2.22 usb_int_enable register (0x0d8) field name rscu bit # reset description usb_busrst_int_ en rw 7 1?b0 1: enable usb_busrst to trigger sysint. usb_bulkonlyrst_ int_en rw 6 1?b0 1: enable usb_bulkonlyrst to trigger sysint. usb_ep0req_int _en rw 5 1?b0 1: enable usb_ ep0req to trigger sysint. usb_cbw_int_e n rw 4 1?b0 1: enable usb_cbw to trigger sysint. usb_wakeup_int_ en rw 3 1?b0 1: enable usb_wakeup to trigger sysint. usb_suspendint_ en rw 2 1?b0 1: enable usb_suspend to trigger sysint. vbus_p__int_e n rw 1 1?b0 1: enable positive of vbus to trigger sysint. vbus_n__int_e n rw 0 1?b0 1: enable negative of vbus to trigger sysint. 6.2.23 usb_int_status/clear register (0x0d9) field name rscu bit # reset description usb_busrst rw 7 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit usb_bulkonlyrst rw 6 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit. usb_ep0req rw 5 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit usb_cbw rw 4 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit usb_wakeup rw 3 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit usb_suspend rw 2 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit vbus_p__int rw 1 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit vbus_n__int rw 0 1?b0 read: 1: indicates this interrupt event occurred write 1: will clear this status bit
INIC-1510 initio corporation 23 6.2.24 gpioa_int_enable register (0x0dc) field name rscu bit # reset description gpioa7_n_inte n rw 5 1?b0 1: enable negative level of gpioa7in to trigger sysint. gpioa6_n_inte n rw 5 1?b0 1: enable negative level of gpioa6in to trigger sysint. gpioa5_n_inte n rw 5 1?b0 1: enable negative level of gpioa5in to trigger sysint. gpioa4_n_inte n rw 4 1?b0 1: enable negative level of gpioa4in to trigger sysint. gpioa3_n_inte n rw 3 1?b0 1: enable negative level of gpioa3in to trigger sysint. gpioa2_n_inte n rw 2 1?b0 1: enable negative level of gpioa2in to trigger sysint. gpioa1_n_inte n rw 1 1?b0 1: enable negative level of gpioa1in to trigger sysint. gpioa7_p_int_e n rw 0 1?b0 1: enable positive level of gpioa7in to trigger sysint. 6.2.25 spi_adr[7:0] register (0x0dd) (for spi-serial flash only) field name rscu bit # reset description spi_adr[7:0] rw 7-0 8?h0 cpu writes the to-be executed spi_adr[7:0] code in this register. 6.2.26 spi_adr[15:8] register (0x0de) (for spi-serial flash only) field name rscu bit # reset description spi_adr[15:8] rw 7-0 8?h0 cpu writes the to-be executed spi_adr[15:8] code in this register. 6.2.27 spi_adr[23:16] register (0x0df) (for spi-serial flash only) field name rscu bit # reset description spi_adr[23:16] rw 7-0 8?h0 cpu writes the to-be executed spi_adr[23:16] code in this register. 6.2.28 gpioa_h enable register (0x0ec) field name rscu bit # reset description reserved r 7 1?b0 reserved gpiob_en rw 6 1?b0 1: enable gpiob group gpioc_en rw 5 1?b0 1: enable gpioc group gpiod_en rw 4 1?b0 1: enable gpiod group gpioe_en rw 3 1?b0 1: enable gpioe group
INIC-1510 initio corporation 24 gpiof_en rw 2 1?b0 1: enable gpiof group reserved r 1 1?b0 reserved reserved r 0 1?b0 reserved 6.2.29 gpiob data register (0x0f2) field name rscu bit # reset description gpioa_data[7:0] rw 7-0 8?b0 write: gpiob_dout[7:0] read: gpiob_din[7:0] 6.2.30 gpiob ctrl register (0x0f3) field name rscu bit # reset description gpiob_ctrl[7:0] rw 7-0 8?b0 1: enable output buffer for the corresponding gpio bit 6.2.31 gpioc data register (0x0f4) field name rscu bit # reset description gpioc_data[7:0] rw 7-0 8?b0 write: gpioc_dout[7:0] read: gpioc_din[7:0] 6.2.32 gpioc ctrl register (0x0f5) field name rscu bit # reset description gpioc_ctrl[7:0] rw 7-0 8?b0 1: enable output buffer for the corresponding gpio bit 6.2.33 gpiod data register (0x0f6) field name rscu bit # reset description gpiod_data[7:0] rw 7-0 8?b0 write: gpiod_dout[7:0] read: gpiod_din[7:0] 6.2.34 gpiod ctrl register (0x0f7) field name rscu bit # reset description gpiod_ctrl[7:0] rw 7-0 8?b0 1: enable output buffer for the corresponding gpio bit 6.2.35 gpioe data register (0x0f8) field name rscu bit # reset description gpioe_data[7:0] rw 7-0 8?b0 write: gpioe_dout[7:0] read: gpioe_din[7:0] 6.2.36 gpioe ctrl register (0x0f9) field name rscu bit # reset description gpioe_ctrl[7:0] rw 7-0 8?b0 1: enable output buffer for the corresponding gpio bit
INIC-1510 initio corporation 25 6.2.37 gpiof data register (0x0fa) field name rscu bit # reset description gpiof_data[7:0] rw 7-0 8?b0 write: gpiof_dout[7:0] read: gpiof_din[7:0] 6.2.38 gpiof ctrl register (0x0fb) field name rscu bit # reset description gpiof_ctrl[7:0] rw 7-0 8?b0 1: enable output buffer for the corresponding gpio bit 7. electrical information: 7.1 absolute maximum ratings symbol parameter min max units vcc power supply -0.3 3.6 v vin input voltage -0.3 vcc+0.3 v vout output voltage -0.3 vcc+0.3 v tstg storage temperature -55 150 c 7.2 recommended operating conditions symbol parameter min typ max units vcc power supply 3.0 3.3 3.6 v vin input voltage 0 - vcc v commercial junction operating temperature 0 25 115 c tj industrial junction operation temperature -40 25 125 c 7.3 general dc characteristics symbol parameter min typ max units iil input leakage current -1 1 a ioz tristate leakage current -1 1 a cin input capacitance 2.8 pf cout output capacitance 2.7 4.9 pf cbid bi-directional buffer capacitance 2.7 4.9 pf 7.4 dc electrical characteristics for 3.3v operation (under vcc=3.0-3.6v, tj=0-115c) symbol parameter conditions min typ max units cmos 0.3*vcc v vil input low voltage cmos schmitt trigger 1.20 0.3*vcc v cmos 0.7*vcc v vih input high voltage cmos schmitt trigger 2.10 v vol output low voltage ioh-2-24ma 0.4 v voh output high voltage ioh=2-24ma 2.4 v ri input pullup/pulldown resistance vil=0/vih=vcc 75 k icc operating supply current vcc=3.3v 50 70 ma
2 t151 3388-010-0061 lqfp64 (7x7x1.4mm) 2005.09.12 a3 1 of 1 10 : 1 footprint 2.0mm package outline 64 1 17 16 48 49 32 33 2005.09.12 2005.09.12 8. packaging specification

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